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general description the max6877/max6878/max6879 multivoltage power trackers/sequencers/supervisors monitor up to three system voltages and provide proper power-up and power-down control for systems requiring voltage track- ing or sequencing. these devices ensure controlled voltage tracking within a specified range or sequencing in the proper order as system power supplies are enabled. the max6877/max6878/max6879 generate all required voltages and timing to control up to three external n-channel pass fets for the out1/out2/ out3 supply voltages (see the selector guide for dif- ferent features of each device). the max6877/max6878/max6879 feature adjustable undervoltage thresholds for each input supply. when all the voltages are above these adjustable thresholds, the devices turn on the external n-channel mosfets to either sequence or track the voltages to the system. during voltage-tracking mode, the voltage at the gate of each mosfet is increased to slowly bring up all supplies at a controlled slew rate. the max6877/ max6878/max6879 feature an autoretry or latch-off mode with capacitor-adjusted timing. these devices also provide a controlled power-down (tracking mode) when the system shuts off in an orderly manner. when an unexpected fault occurs, the outputs are all pulled down simultaneously with an internal 100 ? pulldown to help discharge capactive loads at the mosfet? source. the max6877/max6878/ max6879 feature independent internal charge pumps to fully enhance the external fets for low-voltage drop at highpass current. the max6877 and max6878 also feature a power-good output with a selectable timeout period that can be used for system reset. the max6877/max6878/max6879 are available in small 4mm x 4mm 24-pin and 16-pin thin qfn pack- ages and are fully specified over the -40? to +85? extended operating temperature range. applications multivoltage systems networking systems telecom storage equipment servers/workstations features ? pin-selectable tracking or sequencing control for up to three supply voltages ? capacitor-adjustable power-up/down tracking slew rate ? capacitor-adjustable power-up sequencing delay ? internal charge pumps to enhance external n-channel fets ? capacitor-adjustable timeout period power-good output (max6877/max6878) ? adjustable undervoltage lockout or logic-enable input ? internal 100 ? pulldown for each output to discharge capacitive load quickly ? 0.5v to 5.5v nominal in_/out_ range ? 2.7v to 5.5v operating voltage range ? immune to short voltage transients ? small 4mm x 4mm 24-pin or 16-pin thin qfn packages max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors ________________________________________________________________ maxim integrated products 1 23 24 22 21 8 7 9 abp set2 set1 en/uv 10 v cc gate3 fault pg/rst out2 margin 12 in3 456 17 18 16 14 13 in2 in1 timeout *exposed paddle connected to gnd. slew delay gnd ep* + max6877 set3 out3 3 15 gate1 20 11 ltch/rtr out1 19 12 trk/seq gate2 4mm x 4mm thin qfn top view pin configurations ordering information 19-3771; rev 1; 10/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information continued at end of data sheet. + denotes lead-free package. evaluation kit available selector guide appears at end of data sheet. part temp range pin- package pkg code max6877 etg+ -40? to +85? 24 thin qfn t2444-4 pin configurations continued at end of data sheet.
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc , in1, in2, or in3 = +2.7v to +5.5v, en/ uv = margin = abp, t a = -40? to +85?, unless otherwise specified. typical values are at t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in1, in2, in3, v cc ....................................................-0.3v to +6v abp .....................................-0.3v to the highest of v in1 - v in3 or v cc set1, set2, set3 ....................................................-0.3v to +6v gate1, gate2, gate3 .........................................-0.3v to +12v out1, out2, out3 .................................................-0.3v to +6v ltch /rtr, trk /seq, margin ...............................-0.3v to +6v fault , pg/ rst , en/ uv ...........................................-0.3v to +6v delay, slew, timeout .........................................-0.3v to +6v out_ current....................................................................?0ma gnd current.....................................................................?0ma input/output current (all pins except out_ and gnd) ...........................................................?0ma continuous power dissipation (t a = +70?) 16-pin 4mm x 4mm thin qfn (derate 16.9mw/? above +70?) .............................1349mw 24-pin 4mm x 4mm thin qfn (derate 20.8mw/? above +70?) .............................1667mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? maximum junction temperature .....................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units voltage on abp (the highest of v cc or in_) to ensure that pg/ rst and fault are valid and gate_ = 0v 1.4 operating voltage range v cc voltage on abp (the highest of v cc or in_) to ensure the device is fully operational 2.7 5.5 v supply current i cc v c c = 5.5v , in 1 = in 2 = in 3 = 3.3v , no l oad 1.1 1.8 ma set_ falling, t a = +25 o c 0.4925 0.5 0.5075 set_ threshold range v th set_ falling, t a = -40 o c to +85 o c 0.4875 0.5 0.5125 v set_ threshold hysteresis v th_hys set_ rising 0.5 % set_ input current i set set_ = 0.5v -100 +100 na v en_r input rising 1.286 en/ uv input voltage v en_f input falling 1.22 1.25 1.28 v en/ uv input current i en -5 +5 ? en/ uv input pulse width t en en/ uv falling, 100mv overdrive 7 s delay, timeout output current i d (notes 2, 3) 2.12 2.5 2.88 ? delay, timeout threshold voltage v c c = 3.3v 1.25 v slew output current (note 4) i s 22.5 25 27.5 ? track/sequence slew-rate timebase accuracy sr c slew = 200pf (note 4) -15 +15 % timebase/c slew ratio 100pf < c slew < 1nf (note 4) 104 k ? s l ew - rate accur acy d ur i ng p ow er - u p and p ow er - d ow n c slew = 200pf, abp = 5.5v (note 4) -50 +50 % power-good threshold v th_pg v out_ falling 91.5 92.5 93.5 % (all voltages referenced to gnd, unless otherwise noted.)
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors _______________________________________________________________________________________ 3 note 1: specifications guaranteed for the stated global conditions. 100% production tested at t a = +25? and t a = +85?. specifications at t a = -40? to +85? are guaranteed by design. these devices meet the parameters specified when at least one of v cc , in1/in2/in3 is between 2.7v to 5.5v, while the remaining in1/in2/in3 are between 0 and 5.5v. note 2: a current i d = 2.5? ?5% is generated internally and is used to set the delay and timeout periods and used as a refer- ence for t delay and t timeout . note 3: the total delay is t delay = 200ms + (500k ? x c delay ). leave delay unconnected for 200? delay. the total timeout is t timeout = 200? + (500k ? x c timeout ). leave timeout unconnected for 200? timeout. note 4: a current i s = 25? ?0% is generated internally and used as a reference for t fault , t retry , and slew rate. note 5: during power-up, only the condition out_ < ramp - v trk is checked in order to stop the ramp. however, both conditions out_ < ramp - v trk_f and out_ > ramp + v trk_f cause a fault. during power-down, only the condition out > ramp + v trk is checked in order to stop the ramp. however, both conditions out_ < ramp - v trk_f and out_ > ramp + v trk_f cause a fault (see figure 10). therefore, if out1, out2, and out3 (during power-up tracking and power-down) differ by more than 2 x v trk_f , a fault condition is asserted. note 6: a 100 ? pulldown to gnd activated by a fault condition. see the internal pulldown section. electrical characteristics (continued) (v cc , in1, in2, or in3 = +2.7v to +5.5v, en/ uv = margin = abp, t a = -40? to +85?, unless otherwise specified. typical values are at t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units power-good threshold hysteresis v hys_pg v out_ rising 0.5 % gate_ output high v goh i source = 0.5? in_ + 4.2 in_ + 5.0 in_ + 5.8 v gate_ pullup current i gup during power-up and power-down, v gate_ = 1v 2.5 4 a i gd during power-up and power-down, v gate_ = 5v 2.5 4 a when disabled, v gate_ = 5v, v in_ 2.7v 9.5 gate_ pulldown current i gds when disabled, v gate_ = 5v, v in_ 4v 20 ma set_ to gate_ delay t d-gate set falling, 25mv overdrive 6 s v in_ 2.7v, i sink = 1ma, output asserted 0.3 fault , pg/ rst output low v ol v in_ 4.0v, i sink = 4ma, output asserted 0.4 v tracking differential voltage stop ramp v trk differential between each of the out_ and the ramp voltage during power-up and power-down, figure 10 (note 5) 75 125 180 mv tracking differential fault voltage v trk_f differential between each of the out_ and the ramp voltage, figure 10 (note 5) 200 250 310 mv tracking differential voltage hysteresis 20 % power-low threshold v th_pl out_ falling 125 142 170 mv power-low hysteresis v th_plhys out_ rising 10 mv out to gnd pulldown impedance v abp > 2.7v (note 6) 100 ? margin , trk /seq, ltch /rtr pullup current i in 71013a v il 0.8 margin , trk /seq, ltch /rtr input voltage v ih 2.0 v margin , trk /seq, ltch /rtr glitch rejection 100 ns
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 4 _______________________________________________________________________________________ en/uv v en_r v en_f en/uv bus voltage monitored through en/uv input in_ in1 = 2.5v in2 = 1.8v in3 = 0.7v out_ out1 = 2.5v out2 = 1.8v out3 = 0.7v capacitor- adjusted slew rate pg/rst monitored through set thresholds on set_ inputs t delay t timeout en/uv figure 1. tracking timing diagram in normal mode
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors _______________________________________________________________________________________ 5 en/uv v en_r bus voltage monitored through en/uv input in_ in1 = 2.5v in2 = 1.8v in3 = 0.7v out_ out1 = 2.5v out2 = 1.8v out3 = 0.7v capacitor- adjusted slew rate pg/rst f ault = high monitored through set thresholds on set_ inputs t delay t timeout en/uv in1 goes below set1 threshold v en_f forced into quick shutdown after normal shutdown when in1 goes below its set voltage figure 2. tracking in fast shutdown mode
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 6 _______________________________________________________________________________________ en/uv bus voltage monitored through en/uv input in_ in1 = 2.5v in2 = 1.8v in3 = 0.7v out_ out1 = 2.5v out2 = 1.8v out3 = 0.7v capacitor- adjusted slew rate pg/rst monitored through set thresholds on set_ inputs t delay t delay t delay t timeout en/uv v en_r v en_f figure 3. sequencing in normal mode
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors _______________________________________________________________________________________ 7 in_ in1 = 2.5v in2 = 1.8v in3 = 0.7v monitored through set thresholds on set_ inputs out_ out2 = 1.8v out3 = 0.7v out1 = 3.3v en/uv en/uv bus voltage monitored through en/uv input forced into quick shutdown when out1 falls below 92.5% of in1 out_ forced below v th_pg capacitor- adjusted slew rate pg/rst f ault t delay t delay t delay t timeout v en_r figure 4. sequencing in fast shutdown mode
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 8 _______________________________________________________________________________________ en/uv v en_r v en_f bus voltage monitored through en/uv input in_ in1 = 2.5v in2 = 1.8v in3 = 0.7v out_ out1 = 2.5v out2 = 1.8v out3 = 0.7v capacitor- adjusted slew rate pg/rst = low *any power-down condition before t timeout (pg/rst asserted) causes a shutdown. monitored through set thresholds on set_ inputs t delay *t timeout en/uv figure 5. timing diagram (aborted tracking)
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors _______________________________________________________________________________________ 9 bus voltage monitored through en/uv input in_ in1 = 2.5v in2 = 1.8v in3 = 0.7v out_ out1 = 2.5v out2 = 1.8v out3 = 0.7v monitored through set thresholds on set_ inputs en/uv en/uv pg/rst = low capacitor- adjusted slew rate t delay t delay t delay *t timeout *any power-down condition before t timeout (pg/rst asserted) causes a shutdown. v en_r v en_f figure 6. timing diagram (aborted sequencing)
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 10 ______________________________________________________________________________________ out1 out2 out3 is slow out_ out1 out2 out3 is slow t delay t delay t delay t delay t delay t fault t fault and t retry not to scale all set_ > 0.5v and v cc or in_ 2.7v t fault t retry t delay en/uv f ault figure 8. t fault and t retry timing diagram in sequencing t fault and t retry not to scale all set_ > 0.5v and v cc or in_ 2.7v t fault t fault t retry t delay t delay en/uv v en_r out_ out2 and out3 are waiting out1 is slow out2 and out3 are waiting out1 is slow f ault 125mv figure 7. t fault and t retry timing diagram in tracking
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors ______________________________________________________________________________________ 11 normalized power-good timeout vs. temperature max6877 toc02 temperature ( c) normalized power-good timeout 60 35 -15 10 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 0.75 -40 85 power-good timeout vs. c timeout max6877 toc03 c timeout ( f) power-good timeout (ms) 0.1 0.01 0.001 1 10 100 1000 0.1 0.0001 1 normalized delay timeout vs. temperature max6877 toc05 temperature ( c) normalized delay timeout 60 35 10 -15 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 0.75 -40 85 slew rate vs. c slew max6877 toc06 c slew (pf) slew rate (v/s) 100 1000 100 1000 10,000 10 10 10,000 delay timeout vs. c delay max6877 toc07 c delay ( f) delay timeout (ms) 0.1 0.01 0.001 1 10 100 1000 0.1 0.0001 1 v cc supply current vs. input voltage max6877 toc01 input voltage (v) v cc supply current (ma) 5.0 4.5 4.0 3.5 3.0 0.9 1.0 1.1 1.2 1.3 1.4 0.8 2.5 5.5 t a = +85 c t a = -40 c t a = +25 c normalized set_ threshold vs. temperature max6877 toc04 temperature ( c) normalized set_ threshold 60 35 10 -15 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 1.005 0.995 -40 85 normalized en/uv threshold vs. temperature max6877 toc08 temperature ( c) normalized en_/uv threshold 60 35 10 -15 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 1.005 0.995 -40 85 in_ transient duration vs. in_ threshold overdrive max6877 toc09 in_ threshold overdrive (mv) in_ transient duration ( s) 250 200 150 100 50 3 6 9 12 15 18 21 24 27 30 0 0 300 pg/rst goes low above the curve in_ = 3.3v t ypical operating characteristics (v cc_ = 2.7v to 5.5v, c slew = 200pf, en = margin = abp, t a = +25?, unless otherwise noted.)
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 12 ______________________________________________________________________________________ gate_ output voltage high vs. gate source current max6877 toc11 gate source current ( a) gate_ voltage high (v) 2.5 2.0 1.5 1.0 0.5 1 2 3 4 5 6 7 8 9 10 0 03.0 tracking mode max6877 toc12 10ms/div out1 out2 1v/div en/uv 2v/div out3 sequencing mode max6877 toc13 20ms/div out1 out2 1v/div en/uv 2v/div out3 fast shutdown max6877 toc14 40ms/div out1 out2 1v/div en/uv 2v/div out3 fault 2v/div t ypical operating characteristics (continued) (v cc_ = 2.7v to 5.5v, c slew = 200pf, en = margin = abp, t a = +25?, unless otherwise noted.) gate_ voltage low vs. gate sink current max6877 toc10 gate sink current (ma) gate_ voltage low (v) 9 8 1 2 3 5 6 4 7 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 010 fast shutdown with retry max6877 toc15 100ms/div fault 1v/div out2 2v/div out1 2v/div out3 2v/div threshold error at out1, out1 pulled below 92.5% of in1
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors ______________________________________________________________________________________ 13 pin description pin max6877 max6878 max6879 name function 11v cc optional supply voltage input. connect v cc to an alternate (i.e., always-on) supply if desired. leave v cc unconnected, if not used. v cc allows in_ supplies less than uvlo to be tracked. v cc is internally pulled down by a 100k ? resistor. 221abp internal supply bypass input. bypass abp with a 1? capacitor to gnd. abp maintains the device supply voltage during rapid power-down conditions. 3 set3 442 set2 553 set1 externally adjusted in_ undervoltage lockout threshold. connect set_ to an external resistor-divider network to set the desired undervoltage threshold for each in_ supply (see the typical application circuit ). all set_ inputs must be above the internal set_ threshold (0.5v) to enable tracking or sequencing functionality. 3, 16, 17, 22 ? .c. no connection. not internally connected. 664en/ uv logic-enable input or undervoltage lockout monitor input. en/ uv must be high (en/ uv > v en_r ) to enable voltage tracking or sequencing power-up operation. out_ begins tracking down when en/ uv < v en_f . connect en/ uv to an external resistor-divider network to set the external uvlo threshold. 775 gnd ground 886 delay tracking startup/sequence delay select input. connect a capacitor from delay to gnd to select the desired delay period before tracking is enabled (after all set_ inputs and en/ uv are above their respective thresholds) or between supply sequences. leave delay unconnected for the default 200? delay period. 997 slew slew-rate adjustment input. connect a capacitor from slew to gnd to select the desired out_ slew rate. 10 10 timeout pg/ rst timeout period adjust input. pg/ rst asserts high after the timeout period when all out_ exceed their in_ referenced threshold. connect a capacitor from timeout to gnd to set the desired timeout period. leave timeout unconnected for the default 200? delay period. 11 11 8 ltch/ rtr latch/autor etr y s el ecti on inp u t. d r i ve l tc h /rtr l ow to sel ect the l atch m od e. c onnect l tc h /rtr to abp or l eave unconnected to sel ect autor etr y m od e. l tc h /rtr i s i nter nal l y p ul l ed up to abp thr oug h a 10? cur r ent sour ce. 12 12 9 trk /seq track/sequence select input. drive trk /seq low to enable supply tracking function. connect trk /seq to abp or leave it unconnected to enable supply sequencing. trk /seq is internally pulled to abp through a 10? current source. 13 13 margin margin input, active-low. drive margin low to enable margin mode (see the margin input ( margin ) section). the margin functionality is disabled (returns to normal monitoring mode) after margin returns high. margin is internally pulled up to abp through a 10? current source.
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 14 ______________________________________________________________________________________ pin description (continued) pin max6877 max6878 max6879 name function 14 14 pg/ rst power-good output, open-drain. pg_ rst asserts high t timeout after all out_ voltages exceed the v th_pg thresholds. 15 15 10 fault tracking fault alert output, active low, open-drain. fault asserts low if a tracking failure is present for longer than the selected fault period or if tracking voltages fail by more than ?50mv. fault asserts low if any out_ falls below the corresponding in_ voltage. 16 out3 channel 3 monitored output voltage. connect out3 to the source of an n- channel fet. a fault condition activates a 100 ? pulldown to ground. 17 gate3 gate drive for external n-channel fet. an internal charge pump boosts gate3 to v in3 + 5v to fully enhance the external n-channel fet when power- up is complete. 18 18 11 out2 channel 2 monitored output voltage. connect out2 to the source of an n-channel fet. a fault condition activates a 100 ? pulldown to ground. 19 19 12 gate2 gate drive for external n-channel fet. an internal charge pump boosts gate2 to v in2 + 5v to fully enhance the external n-channel fet when power- up is complete. 20 20 13 out1 channel 1 monitored output voltage. connect out1 to the source of an n-channel fet. a fault condition activates a 100 ? pulldown to ground. 21 21 14 gate1 gate drive for external n-channel fet. an internal charge pump boosts gate1 to v in1 + 5v to fully enhance the external n-channel fet when power- up is complete. 22 in3 23 23 15 in2 24 24 16 in1 supply input voltage. in1, in2, or in3 must be greater than the internal undervoltage lockout (v abp = 2.7v) to enable the tracking or sequencing functionality. each in_ input is simultaneously monitored by set_ inputs to ensure all supplies have stabilized before power-up is enabled. if in_ is connected to ground or left unconnected and set_ is above 0.5v, then no- sequencing control is performed on that channel. each in_ is internally pulled down by a 100k ? resistor. ep ep ep ep exposed paddle. connect exposed paddle to ground.
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors ______________________________________________________________________________________ 15 control logic tracking monitors pg circuit charge pump gate controller out1 out2 out3 in1 in2 in3 v ref in1 in1 in2 v cc in3 abp gate1 out1 gate2 out2 gate3 out3 pg/rst delay l tch/rtr slew margin v bus en/uvlo set3 set2 in2 set1 gnd c slew timeout c timeout to load in1 max6877 in3 trk/seq f ault comp comp comp comp in3 to out3 control block in2 to out2 control block ramp generator internal v cc /uvlo functional diagram
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 16 ______________________________________________________________________________________ detailed description the max6877/max6878/max6879 multivoltage power trackers/ sequencers/supervisors monitor up to three system voltages and provide proper power-up and power-down control for systems requiring voltage tracking or sequencing. these devices ensure con- trolled voltage tracking with a specified range or sequencing in the proper order as system power sup- plies are enabled. the max6877/max6878/max6879 generate all required voltages and timing to control up to three external n-channel pass fets for the out1/out2/out3 supply voltages (see the selector guide for different features of each device.) the max6877/max6878/max6879 feature adjustable undervoltage thresholds for each input supply. when all the voltages are above these adjusted thresholds, the devices turn on the external n-channel mosfets to either sequence or track the voltages to the system. during the voltage-tracking mode, the voltage at the gate of each mosfet is increased to slowly bring up all supplies at a controlled slew rate. the voltage at the source (output) of each mosfet is internally compared to a control ramp to maintain a low differential between each monitored supply. tracking is dynamically adjust- ed to force all outputs to track within 125mv of the ref- erence ramp. if for any reason any supplies fail to track within ?50mv of the reference ramp, the fault out- put is asserted, the power-up mode is terminated, and all outputs are quickly powered off. in sequencing mode, the outputs are turned on one after the other, out1 first and out3 last. the max6877/max6878/ max6879 feature an autoretry or latch-off mode with capacitor-adjusted timing. these devices also provide a controlled power-down (tracking mode) when the system shuts off in an orderly manner. when an unexpected fault occurs, the outputs are all pulled down simultaneously with an internal 100 ? pulldown to help discharge capacitive loads at the mosfet? source. the max6877/max6878/max6879 feature independent internal charge pumps to fully enhance the external fets for low-voltage drops at highpass currents. the max6877/max6878 also feature a power-good output with a selectable timeout period that can be used for system reset. the max6877/max6878/max6879 monitor up to three voltages. devices may be configured to exclude any in_. to disable the tracking or sequencing operation of any in_, connect the in_ to ground (or leave uncon- nected) and connect set_ to a voltage greater than 0.5v. the channel exclusion feature adds more flexibili- ty to the device in a variety of different applications. as an example, the max6877 can track or sequence two voltages using in1 and in2 while in3 is left disabled. powering the max6877/max6878/max6879 these devices derive power from either the in1, in2, or in3 voltage inputs or v cc (see the functional diagram ). v cc or one of the in_ inputs must be at least +2.7v to ensure full device operation. the highest input voltage on in1/in2/in3 or v cc sup- plies power to the devices. internal hysteresis ensures that the supply input that initially powers these devices continues to power the max6877/max6878/max6879 when multiple input voltages are within 100mv (typ) of each other. abp abp powers the analog circuitry. bypass abp to gnd with a 1? ceramic capacitor installed as close to the device as possible. abp takes the highest voltage of in_ or v cc . do not use abp to provide power to exter- nal circuitry. abp maintains the device supply voltage during rapid power-down conditions. tracking and sequencing modes ( trk /seq) to enable the power-up/power-down voltage-tracking operation, drive trk /seq low (connect trk /seq to gnd). to enable power-up sequencing and power- down tracking functions, drive trk /seq high (connect trk /seq to abp) or leave it unconnected. trk /seq is internally pulled to abp through a 10? current source (see figures 1 and 3). tracking to operate in tracking mode, connect trk /seq to gnd. when v en/ uv > 1.25v and all set_ inputs are above the internal set_ threshold (0.5v), the tracking process is initiated. the max6877/max6878/max6879 generate an internal reference ramp voltage that drives the control loops for the tracked voltages. the tracking functionality is monitored with a comparator control block for each output (see the functional diagram ). the comparators monitor each out_ voltage with respect to the common reference ramp voltage to ensure the out_ voltages stay within 125mv of the ref- erence ramp, monitor each tracked output voltage with respect to its source input voltage, and monitor each output voltage with respect to gnd during power- up/retry cycles. if for any reason any supplies fail to track within ?50mv of the reference ramp, the fault output is asserted, the power-up mode is terminated, and all outputs are quickly powered off.
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors ______________________________________________________________________________________ 17 during ramp up, if an out_ voltage is less than the ref- erence ramp voltage by more than 125mv, the control loop dynamically stops the control ramp voltage from rising until the slow out_ voltage catches up. if an out_ voltage is greater or less than the reference ramp voltage by more than 250mv, a fault is signaled and a power-down phase is initiated. the slew rate for the reference ramp voltage is capaci- tor adjustable. connect a capacitor from slew to ground to select the desired out_ slew rate. when all out_ voltages have exceeded the v th_pg percentage of the in_ voltage (external n-channel fet is saturated), pg/ rst asserts high after t timeout indicating success- ful tracking. sequencing the sequencing operation can be initiated after all input conditions for power-up are met v en/ uv > 1.25v and all set_ inputs are above the internal set_ thresh- old (0.5v). in sequencing mode, the outputs are turned on sequentially, out1 first and out3 last. before turn- ing on each channel, a delay period occurs as in figure 3 (programmable by connecting a capacitor from delay to ground). the power-up phase for each channel ends when its output voltage exceeds a fixed percentage (v th_pg ) of the corresponding in_ voltage. when all channels have exceeded these thresholds, pg/ rst asserts high after t timeout , indicating a suc- cessful sequence. if there is a fault condition during the initial power-up sequence, the process is aborted. when powering down, all outputs turn off simultaneous- ly, tracking each other. no reverse power-down sequencing occurs. power-up and power-down during power-up, the out_ is forced to follow the internal reference ramp voltage by an internal loop that controls the gate_ of the external mosfet. this phase must be completed within the adjustable fault timeout period; oth- erwise, the part forces a shutdown on all gate_. once the power-up is completed, a power-down phase can be initiated by forcing v en/ uv below v en_f . the reference voltage ramp ramps down at the capacitor- adjusted slew rate. the control-loop comparators moni- tor each out_ voltage with respect to the common reference ramp voltage. during ramp down, if an out_ voltage is greater than the reference ramp voltage by more than v trk , the control loop dynamically stops the control ramp voltage from decreasing until the slow out_ voltage catches up. if an out_ voltage is greater or less than the reference ramp voltage by more than v trk_f , a fault is signaled and the fast-shutdown mode is initiated. in fast-shutdown mode, a 100 ? pulldown resistor is connected from out_ to gnd to quickly dis- charge capacitance at out_ and gate _ is pulled low with a strong i gds current (see figures 2 and 4). figures 5 and 6 show aborted tracking and sequencing modes. when en/ uv goes low before t timeout expires, all the outputs go low and the device goes into fast shutdown. internal pulldown to ensure that the out_ voltages are not held high by a large output capacitance after a fault has occurred, there is a 100 ? internal pulldown at out_. the pull- down ensures that all out_ voltages are below v th_pl (referenced to gnd) before power-up cycling is initiat- ed. the internal pulldown also ensures a fast discharge of the output capacitor during fast shutdown and fault modes. the pulldowns are not present during normal operation. stability comment no external compensation is required for tracking or slew-rate control. inputs in1/in2/in3 the highest voltage on v cc , in1, in2, or in3 supplies power to the device. the undervoltage threshold for each in_ supply is set with an external resistor-divider from each in_ to set_ to ground. undervoltage lockout threshold inputs (set_) the max6877 features three and the max6878/ max6879 feature two externally adjustable in_ under- voltage lockout (uvlo) thresholds (set1, set2, set3) to enable sequencing/tracking functionality. the undervolt- age threshold for each in_ supply is set with an exter- nal resistor-divider from each in_ to set_ to ground (see figure 9). all set_ inputs must be above the inter- nal set_ threshold (0.5v) to enable tracking/sequenc- ing functionality. use the following formula to set the uvlo threshold: v in_ = v th (r1 + r2) / r2 where v in_ is the undervoltage lockout threshold and v th is the 500mv set threshold. margin input ( m m a a r r g g i i n n ) margin allows system-level testing while power sup- plies are below the normal ranges as adjusted by the set_ inputs. drive margin low before varying system
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 18 ______________________________________________________________________________________ voltages below the adjusted thresholds to avoid signal- ing an error. the state of pg/ rst and fault outputs does not change while margin is low. pg/ rst , fault , and all monitoring functions are disabled while margin is low. margin makes it possible to vary the sup plies without a need to adjust the thresholds to pre- vent tracker/sequencer alerts or faults. drive margin high or leave it unconnected for normal operating mode. slew-rate control input (slew) the reference ramp voltage slew rate during any con- trolled power-up/down phase can be programmed in the 90v/s to 950v/s range by connecting a capacitor (c slew ) from slew to ground. use the following for- mula to calculate the typical slew rate: slew rate = (9.35 x 10 -8 )/ c slew where slew rate is in v/s and c slew is in farads. the capacitor at c slew also sets the fault timeout period (t fault ) and fault retry timeout period (t retry ) (see table 1). for example, if c slew = 100pf, we have t retry = 350ms, t fault = 21.91ms, slew rate = 935v/s. for example, if c slew = 1nf, we have t retry = 3.5s, t fault = 219ms, slew rate = 93.5v/s. c slew is the capacitor on the slew pad, and must be large enough to make the parasitic capacitance negli- gible. c slew should be in the range of 100pf < c slew < 1nf. limiting inrush current the capacitor connected at slew controls the out_s slew rate, thus controlling the inrush current required to charge the load capacitor at the outputs (out_). using the programmed slew rate, limit the inrush current by using the following formula: i inrush = c out x sr where i inrush is in amperes, c out is in farads, and sr is in v/s. delay time input (delay) to adjust the desired delay period (t delay ) before tracking/sequencing is enabled, connect a capacitor (c delay ) between delay to ground (see figures 1 to 8). the selected delay time is also enforced when en/ uv rises from low to high when all the input voltages (in1/in2/in3) are present. use the following formula to calculate the delay time: t delay = 200? + (500k ? x c delay ) where t delay is in ? and c delay is in farads. leave delay unconnected for the default 200? delay. timeout period input (timeout) these devices feature a pg/ rst timeout period. connect a capacitor (c timeout ) from timeout to ground to program the pg/ rst timeout period. after all out_ outputs exceed their in_ referenced thresholds (v th_pg ), pg/ rst remains low for the selected timeout period, t timeout (see figure 3): t timeout = 200? + (500k ? x c timeout ) where t timeout is in ? and c timeout is in farads. leave timeout unconnected for the default 200? timeout delay. logic-enable input (en/ uv ) drive logic en/ uv input above v en_r to initiate voltage tracking/sequencing during the power-up operation. drive logic en/ uv below v en_f to initiate tracking power-down operation. connect en/ uv to an external resistor-divider network to set the external undervoltage lockout threshold. out1/out2/out3 the max6877 monitors three and max6878/max6879 monitor two out_ outputs to control the tracking/ sequencing performance. after the internal supply (abp) exceeds the minimum voltage (2.7v) require- ments, en/ uv > v en_r , and in1/in2/in3 are all greater than their adjusted set_ thresholds, out1/out2/out3 begin to track or sequence. table 1. c slew timing formulas time period formulas slew rate (9.35 x 10 -8 ) / c slew t retry 3.506 x 10 9 x c slew t fault 2.191 x 10 8 x c slew in_ r1 r2 v in_ set_ max6877 max6878 max6879 figure 9. setting the undervoltage (uvlo) thresholds
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors ______________________________________________________________________________________ 19 during fault conditions, an internal pulldown resistor (100 ? ) on out_ is enabled to help discharge load capacitance (100 ? is connected for fast power-down control). outputs gate_ the max6877/max6878/max6879 feature up to three gate_ outputs to drive up to three external n-channel fet gates. the following con ditions must be met before gate_ begins enhancing the external n-channel fet_: 1) all set_ inputs (set1?et3) are above their 0.5v thresholds. 2) at least one in_ input or v cc is above the minimum operating voltage (2.7v). 3) en/ uv > 1.25v. at power-up mode, gate_ voltages are enhanced by control loops so that all out_ voltages track together at a capacitor-adjusted slew rate. each gate_ is internal- ly pulled up to 5v above its relative in_ voltage to fully enhance the external n-channel fet when power-up is complete. fault the max6877/max6878/max6879 include an open- drain, active-low tracking fault alarm output ( fault ). fault asserts low when a power-up phase is not com- pleted within the specified fault period or if out_ volt- ages are more than v trk_f . the fault time period (t fault ) is set through the capaci- tor at slew (c slew ). use the following formula to esti- mate the fault timeout period: t fault = 2.191 x 10 8 x c slew power-supply tracking operation should be completed within the selected fault timeout period (t fault ). the total tracking time is extended when the devices must vary the control slew rate to allow slow supplies to catch up. if the external fet is too small (r ds is too high for the selected load current and in_ source cur- rent), the out_ voltage may never reach the control ramp voltage. for a slew rate of 935v/s, a fault is sig- naled if all outputs have not stabilized within 22ms. for a slew rate of 93.5v/s, a fault is signaled if tracking takes too long (more than 219ms). during power-up, only the condition, out_ < ramp - v trk , is monitored in order to stop the ramp. however, both conditions out < ramp - v trk_f and out_ > ramp + v trk_f cause a fault. during power-down, only the condition out > ramp + v trk is checked in order to stop the ramp. however, both conditions out_ < ramp - v trk_f and out_ > ramp + v trk_f cause a fault (see figure 10). out1, out2, and out3 are tracked within v trk_f (mv) (power-up tracking and power-down), and if they differ by more than 2 x v trk_f a fault condition is asserted. retry time period (t retry ) is defined as 16 x t fault . to calculate the retry time period use the following formula: t retry = 3.506 x 10 9 x c slew where t retry is in ? and c slew is in farads. autoretry and latch-off functions ( ltch /rtr) the max6877/max6878/max6879 feature latch-off or autoretry modes to power-on again after a fault condi- tion has been detected. connect ltch /rtr to ground to set the latch-off mode. to select autoretry mode, connect ltch /rtr to abp or leave unconnected. 250mv down = f ault threshold 250mv down = f ault threshold 125mv down = stop ramp threshold 125mv up = stop ramp threshold 250mv up = f ault threshold 250mv up = f ault threshold reference ramp reference ramp power-up power-down figure 10. stop ramp fault window during power-up and power-down
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 20 ______________________________________________________________________________________ when a fault is detected, for a period of t retry , gate_ remains off and the 100 ? pulldowns are turned on. after the t retry period, the device waits t delay and retries power-up if all power-up conditions are met (see figure 8). these include all v set_ > 0.5v, en/ uv > v en_r , out_ voltages < v th_pl . the autoretry period, t retry , is a function of c slew ; see table 1. when the device is in latch mode and a fault occurs, fault asserts and all outputs are latched off. to unlatch out_ after a fault disappears, cycle en/ uv or cycle v cc and the inputs (in_) below the 2.7v uvlo threshold. after en/ uv goes high, the device waits a t retry period then tries to power-up again. if v cc and all in_ are cycled below 2.7v, the device tries to power- up immediately. power-good output (pg/ rst ) the max6877/max6878 include a power-good (pg/ rst ) output. pg/ rst is an open-drain output and requires an external pullup resistor. all the out_ outputs must exceed their in_ referenced thresholds (in_ x v th_pg ) for the selected reset timeout period t timeout (see the timeout period input sec- tion) before pg/ rst asserts high. pg/ rst stays low for the selected reset timeout period (t timeout ) after all the out_ voltages exceed their in_ referenced thresh- olds. pg/ rst goes low when v set_ < v th or v en/ uv < v en_r (see figure 3). applications information mosfet selection the external pass mosfet is connected in series with the sequenced power-supply source. since the load current and the mosfet drain-to-source impedance (r ds ) determine the voltage drop, the on characteris- tics of the mosfet affect the load supply accuracy. the max6877/max6878/max6879 fully enhance the external mosfet out of its linear range to ensure the lowest drain-to-source on-impedance. for highest sup- ply accuracy/lowest voltage drop, select a mosfet with an appropriate drain-to-source on-impedance with a gate-to-source bias of 4.5v to 6.0v. layout and bypassing for better noise immunity, bypass each of the in_ inputs to gnd with 0.1? capacitors installed as close to the device as possible. bypass abp to gnd with a 1? capacitor installed as close to the device as possi- ble. abp is an internally generated voltage and must not be used to supply power to external circuitry. selector guide part channel timeout selectable pg/ rst margin v cc max6877 3 yes yes yes yes max6878 2 yes yes yes yes max6879 2 no no no no
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors ______________________________________________________________________________________ 21 set1 in1 0.1 f 0.1 f 0.1 f 1 f in1 in2 in3 set2 set3 en/uv out1 out1 out2 out3 abp slew delay timeout gnd trk/seq out2 out3 fault pg/rst v bus in2 in3 gate1 gate2 gate3 margin ltch/rtr v cc max6877 t ypical application circuit
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors 22 ______________________________________________________________________________________ 4mm x 4mm thin qfn top view 4mm x 4mm thin qfn 15 16 14 13 6 5 7 set2 en/uv 8 abp out2 trk/seq gate2 12 gate1 4 12 11 9 in2 in1 ltch/rtr slew delay gnd max6879 set1 fault 3 10 out1 *exposed paddle connected to gnd. ep* ep* 23 24 22 21 8 7 9 abp set2 set1 en/uv 10 v cc n.c. fault pg/rst out2 margin 12 n.c. 456 17 18 16 14 13 in2 in1 timeout slew delay gnd max6878 n.c. n.c. 3 15 gate1 20 11 ltch/rtr out1 19 12 trk/seq gate2 ++ pin configurations (continued) chip information process: bicmos ordering information (continued) part temp range pin- package pkg code max6878 etg+ -40? to +85? 24 thin qfn t2444-4 max6879 ete+ -40? to +85? 16 thin qfn t1644-4 + denotes lead-free package.
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors ______________________________________________________________________________________ 23 pa c kag e information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm
max6877/max6878/max6879 dual-/triple-voltage, power-supply t rackers/sequencers/supervisors maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products is a registered trademark of maxim integrated products, inc. heaney package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm

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